Design of an image sampling and processing system based on FPGA and USB bus

ZHOU Jianbo; GONG Xianfeng; WANG Zhangsong; SUN Honglin

doi:10.13374/j.issn1001-053x.2006.09.018

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ZHOU Jianbo, GONG Xianfeng, WANG Zhangsong, SUN Honglin. Design of an image sampling and processing system based on FPGA and USB bus[J]. Chinese Journal of Engineering, 2006, 28(9): 886-889. doi: 10.13374/j.issn1001-053x.2006.09.018

Citation:

ZHOU Jianbo, GONG Xianfeng, WANG Zhangsong, SUN Honglin. Design of an image sampling and processing system based on FPGA and USB bus[J]. Chinese Journal of Engineering, 2006, 28(9): 886-889. doi: 10.13374/j.issn1001-053x.2006.09.018

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Design of an image sampling and processing system based on FPGA and USB bus

doi: 10.13374/j.issn1001-053x.2006.09.018

Mechanical Engineering School, University of Science and Technology Beijing, Beijing 100083, China

Received Date: 2005-07-16
Rev Recd Date: 2005-09-07

Available Online: 2021-08-24

Abstract

Abstract

This paper designed an high-speed image sampling and processing system based on FPGA, whose image-sampling frequency was 13.5 MHz. In the system the video A/D chip SAA7111A was employed to convert video data into digital signal, and the digital signal was storied in RAM by FPGA for next processing to obtain the useful data. In addition, the EZUSB2131Q chip was used to transmit the processed data between PC and FPGA.
- video image,
- signal processing,
- FPGA,
- VHDL,
- EZUSB,
- video A/D